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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-29 17:53:25 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-12-26 11:00:05 +0100 |
| commit | cf919770d05a9b7d10b1609d0b66bc5db8e78a3e (patch) | |
| tree | d2e3174992ca8522c3519038eb859603f782f47b /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r9a09g011: Add PWM clock and reset entries (diff) | |
| download | linux-rng-cf919770d05a9b7d10b1609d0b66bc5db8e78a3e.tar.xz linux-rng-cf919770d05a9b7d10b1609d0b66bc5db8e78a3e.zip | |
clk: renesas: r8a779g0: Fix OSC predividers
According to the table in Note 5 for the OSC clock in Table 8.1.4e
("Lists of CPG clocks generated from PLL5") of the R-Car V4H Series
Hardware User's Manual Rev. 0.54, the predividers for the OSC clock are
16 resp. 32 when using a 16.66 resp. 33.33 MHz external crystal.
Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/dcd572acc584c237f70d2309e038f25040236a87.1669740722.git.geert+renesas@glider.be
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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