diff options
| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-12-05 14:59:50 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-12-27 09:42:44 +0100 |
| commit | d459f557ad76f449687e76fcb94f1009551dd669 (patch) | |
| tree | c54f7e7bf2d82658ff837da3db44a85f2a332716 /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r8a779g0: Add display related clocks (diff) | |
| download | linux-rng-d459f557ad76f449687e76fcb94f1009551dd669.tar.xz linux-rng-d459f557ad76f449687e76fcb94f1009551dd669.zip | |
clk: renesas: r9a09g011: Add TIM clock and reset entries
Add Compare-Match Timer (TIM) clock and reset entries to CPG
driver.
The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has
full control of channels 0 to 7, and channels 24 to 31. Therefore
Linux is only allowed to use channels 8 to 23.
The TIM has shared peripheral clock with other modules, so mark it
as critical clock.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221205145955.391526-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions