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author | 2023-09-05 15:38:35 +0530 | |
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committer | 2023-09-05 12:25:14 -0400 | |
commit | df8fdd01c98b99d04915c04f3a5ce73f55456b7c (patch) | |
tree | 84e559ff889c6a1c008394f86649dcd10f4ee2d5 /scripts/generate_rust_analyzer.py | |
parent | counter: chrdev: fix getting array extensions (diff) | |
download | linux-rng-df8fdd01c98b99d04915c04f3a5ce73f55456b7c.tar.xz linux-rng-df8fdd01c98b99d04915c04f3a5ce73f55456b7c.zip |
counter: microchip-tcb-capture: Fix the use of internal GCLK logic
As per the datasheet, the clock selection Bits 2:0 – TCCLKS[2:0] should
be set to 0 while using the internal GCLK (TIMER_CLOCK1).
Fixes: 106b104137fd ("counter: Add microchip TCB capture counter")
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Link: https://lore.kernel.org/r/20230905100835.315024-1-dharma.b@microchip.com
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions