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| author |   Marc Zyngier <maz@kernel.org> | 2022-07-01 15:31:20 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-07-01 15:31:20 +0100 |
| commit | ee4aae577721035b21fcb9f9359825e9626edcfd (patch) | |
| tree | e8e57298f8143343133a078fc0c370c1a8f1fe75 /scripts/generate_rust_analyzer.py | |
| parent | Linux 5.19-rc3 (diff) | |
| parent | irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling (diff) | |
| download | linux-rng-ee4aae577721035b21fcb9f9359825e9626edcfd.tar.xz linux-rng-ee4aae577721035b21fcb9f9359825e9626edcfd.zip | |
Merge branch irq/plic-edge-fixes into irq/irqchip-next
* irq/plic-edge-fixes:
: .
: Work around broken PLIC implementations that deal pretty
: badly with edge-triggered interrupts. Flag two implementations
: as affected.
: .
irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC
irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions