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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-22 13:50:34 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:44:19 +0200 |
| commit | f7444f0fde1f51229c5a4c796730b5caaae0bb6d (patch) | |
| tree | b4ff08792e7298666a185c33cef6c50044406710 /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type (diff) | |
| download | linux-rng-f7444f0fde1f51229c5a4c796730b5caaae0bb6d.tar.xz linux-rng-f7444f0fde1f51229c5a4c796730b5caaae0bb6d.zip | |
clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
All users of the fixed default PLL2/3/4/6 clock types have been
converted to fixed or variable fractional PLL clock types.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/c0229eb3518444f61173c6fb83bdcedb058dd079.1721648548.git.geert+renesas@glider.be
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions