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authorE Shattow <e@freeshell.de>2025-05-02 03:30:42 -0700
committerConor Dooley <conor.dooley@microchip.com>2025-05-15 21:08:27 +0100
commit59404dceb303712faa9507b27c6fb14d8629c528 (patch)
tree14fd4144299ae2b0e771e8a4eab63f81a8c8b634 /scripts/lib/kdoc/kdoc_files.py
parentriscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg (diff)
downloadlinux-rng-59404dceb303712faa9507b27c6fb14d8629c528.tar.xz
linux-rng-59404dceb303712faa9507b27c6fb14d8629c528.zip
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
Use qspi flash read-delay and spi-max-frequency settings compatible with U-Boot bootloader. Observations from testing on Pine64 Star64 hardware within U-Boot bootloader and read-delay=2 are spi-max-frequency less than 49.8MHz fails to write, corrupt data writes at 25MHz to 49.799999MHz, and valid data writes at 49.8MHz to 100MHz (not tested above 100MHz). No valid spi-max-frequency was found for 1<read-delay<=3 and corrupt data with read-delay=3. Looking around the Linux codebase it is common to see read-delay 2 cycles with spi-max-frequency 100MHz and testing confirms this to work in both U-Boot and Linux. Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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