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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-04-01 19:37:49 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-04-10 20:15:04 +0300 |
| commit | efaa1177c31be89483dfd3919348b3535f602b5e (patch) | |
| tree | 472604ec7ab8af8cdbf11898797d6d36c0db01ad /scripts/lib/kdoc/kdoc_output.py | |
| parent | drm/i915/wm: convert i9xx_wm.c internally to struct intel_display (diff) | |
| download | linux-rng-efaa1177c31be89483dfd3919348b3535f602b5e.tar.xz linux-rng-efaa1177c31be89483dfd3919348b3535f602b5e.zip | |
drm/i915: Apply the combo PLL frac w/a on DG1
DG1 apparently needs the combo PLL fractional divider w/a
with 38.4 MHz refclk as well. This isn't listed in bspec, but
looking at the hsd it looks like it was possibly just missed
due to no one having a DG1 around at the time.
This gives us slightly more accurate clocks on DG1.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250401163752.6412-2-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_output.py')
0 files changed, 0 insertions, 0 deletions