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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2025-06-04 10:50:42 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-06-04 10:50:42 -0500 |
| commit | 05cf00aa05afed0d6808cce6654ef8be457fb6bb (patch) | |
| tree | ef9470ba6b660beb077f8dc8f041523814b752b7 /scripts/lib/kdoc/kdoc_parser.py | |
| parent | Merge branch 'pci/controller/mvebu' (diff) | |
| parent | PCI: qcom: Add support for IPQ5018 (diff) | |
| download | linux-rng-05cf00aa05afed0d6808cce6654ef8be457fb6bb.tar.xz linux-rng-05cf00aa05afed0d6808cce6654ef8be457fb6bb.zip | |
Merge branch 'pci/controller/qcom'
- Add OF support for parsing DT 'eq-presets-<N>gts' property for lane
equalization presets (Krishna Chaitanya Chundru)
- Read Maximum Link Width from the Link Capabilities register if DT lacks
'num-lanes' property (Krishna Chaitanya Chundru)
- Add Physical Layer 64 GT/s Capability ID and register offsets for 8, 32,
and 64 GT/s lane equalization registers (Krishna Chaitanya Chundru)
- Add generic dwc support for configuring lane equalization presets
(Krishna Chaitanya Chundru)
- Add DT and driver support for PCIe on IPQ5018 SoC (Nitheesh Sekar)
* pci/controller/qcom:
PCI: qcom: Add support for IPQ5018
dt-bindings: PCI: qcom: Add IPQ5018 SoC
PCI: dwc: Add support for configuring lane equalization presets
PCI: Add lane equalization register offsets
PCI: dwc: Update pci->num_lanes to maximum supported link width
PCI: of: Add of_pci_get_equalization_presets() API
Diffstat (limited to 'scripts/lib/kdoc/kdoc_parser.py')
0 files changed, 0 insertions, 0 deletions