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| author |   Chris Packham <chris.packham@alliedtelesis.co.nz> | 2019-09-27 11:28:19 +1200 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-08 11:49:07 +0200 |
| commit | 042fa3dcd5e9884119afdba4d2691c3842e86558 (patch) | |
| tree | e59d824e21852333b3b2e55b92a942260246847e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg (diff) | |
| download | linux-rng-042fa3dcd5e9884119afdba4d2691c3842e86558.tar.xz linux-rng-042fa3dcd5e9884119afdba4d2691c3842e86558.zip | |
ARM: dts: mvebu: add sdram controller node to Armada-38x
The Armada-38x uses an SDRAM controller that is compatible with the
Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x
is 32/16). The SDRAM controller registers are the same between the two
SoCs.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions