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| author |   Neil Armstrong <narmstrong@baylibre.com> | 2019-03-07 15:14:55 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-04-01 10:45:11 +0200 |
| commit | 34775209ba37bff3b4e60ddee0a2d69966146a5d (patch) | |
| tree | 56e95653b6f0ae3dfc4da6b7cc362d450e52470a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL (diff) | |
| download | linux-rng-34775209ba37bff3b4e60ddee0a2d69966146a5d.tar.xz linux-rng-34775209ba37bff3b4e60ddee0a2d69966146a5d.zip | |
clk: meson-g12a: add PCIE PLL clocks
Add the PCIe reference clock feeding the USB3 + PCIE combo PHY.
This PLL needs a very precise register sequence to permit to be locked,
thus using the specific clk-pll pcie ops.
The PLL is then followed by :
- a fixed /2 divider
- a 5-bit 1-based divider
- a final /2 divider
This reference clock is fixed to 100MHz, thus only a single PLL setup
is added.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-4-narmstrong@baylibre.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions