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| author |   Vladimir Oltean <vladimir.oltean@nxp.com> | 2025-01-14 18:47:20 +0200 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2025-01-15 13:22:23 -0800 |
| commit | 5c71729ab92c7e710d48ed93043a2d1e35cc8d3c (patch) | |
| tree | 36cb838dab1ec611e23b4045cf0957075f8bcf11 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | selftests: net: Adapt ethtool mq tests to fix in qdisc graft (diff) | |
| download | linux-rng-5c71729ab92c7e710d48ed93043a2d1e35cc8d3c.tar.xz linux-rng-5c71729ab92c7e710d48ed93043a2d1e35cc8d3c.zip | |
net: pcs: xpcs: fix DW_VR_MII_DIG_CTRL1_2G5_EN bit being set for 1G SGMII w/o inband
On a port with SGMII fixed-link at SPEED_1000, DW_VR_MII_DIG_CTRL1 gets
set to 0x2404. This is incorrect, because bit 2 (DW_VR_MII_DIG_CTRL1_2G5_EN)
is set.
It comes from the previous write to DW_VR_MII_AN_CTRL, because the "val"
variable is reused and is dirty. Actually, its value is 0x4, aka
FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, DW_VR_MII_PCS_MODE_C37_SGMII).
Resolve the issue by clearing "val" to 0 when writing to a new register.
After the fix, the register value is 0x2400.
Prior to the blamed commit, when the read-modify-write was open-coded,
the code saved the content of the DW_VR_MII_DIG_CTRL1 register in the
"ret" variable.
Fixes: ce8d6081fcf4 ("net: pcs: xpcs: add _modify() accessors")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/20250114164721.2879380-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions