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| author |   Jun Lei <Jun.Lei@amd.com> | 2019-05-27 14:15:27 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:14 -0500 |
| commit | 6e17b5b8a846850d73e06dc778e7d5c3ef0423f9 (patch) | |
| tree | 49634762b7d6c7296eab3fd363f381a0ac3eb01b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Rework CRTC color management (diff) | |
| download | linux-rng-6e17b5b8a846850d73e06dc778e7d5c3ef0423f9.tar.xz linux-rng-6e17b5b8a846850d73e06dc778e7d5c3ef0423f9.zip | |
drm/amd/display: update DCN2 uclk switch time
[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated
[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions