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| author |   Alexey Kardashevskiy <aik@ozlabs.ru> | 2017-02-22 15:43:59 +1100 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2017-03-09 19:07:12 +1100 |
| commit | 7aafac11e308d37ed3c509829bb43d80c1811ac3 (patch) | |
| tree | c6e1a9bfe6c069d3cbf4ee52919d50df3249012f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | selftests/powerpc: Replace stxvx and lxvx with stxvd2x/lxvd2x (diff) | |
| download | linux-rng-7aafac11e308d37ed3c509829bb43d80c1811ac3.tar.xz linux-rng-7aafac11e308d37ed3c509829bb43d80c1811ac3.zip | |
powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested
The IODA2 specification says that a 64 DMA address cannot use top 4 bits
(3 are reserved and one is a "TVE select"); bottom page_shift bits
cannot be used for multilevel table addressing either.
The existing IODA2 table allocation code aligns the minimum TCE table
size to PAGE_SIZE so in the case of 64K system pages and 4K IOMMU pages,
we have 64-4-12=48 bits. Since 64K page stores 8192 TCEs, i.e. needs
13 bits, the maximum number of levels is 48/13 = 3 so we physically
cannot address more and EEH happens on DMA accesses.
This adds a check that too many levels were requested.
It is still possible to have 5 levels in the case of 4K system page size.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions