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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-01-27 17:31:59 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:06 +0100 |
| commit | 7f22a298d926664b51fcfe2f8ea5feb7f8b79952 (patch) | |
| tree | 7f70a653bc2589bc95821350ce2e315cc26c4cd7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a09g047: Add SDHI clocks/resets (diff) | |
| download | linux-rng-7f22a298d926664b51fcfe2f8ea5feb7f8b79952.tar.xz linux-rng-7f22a298d926664b51fcfe2f8ea5feb7f8b79952.zip | |
clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock
source for HP is derived from PLL6 divided by 2. Correct the
implementation by configuring HP as a fixed clock source instead of a
MUX.
The `CPG_PL6_ETH_SSEL' register, which is available on the RZ/G2UL SoC,
is not present on the RZ/Five SoC, necessitating this change.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Cc: stable@vger.kernel.org
Reported-by: Hien Huynh <hien.huynh.px@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250127173159.34572-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions