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| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2025-01-15 18:59:26 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:06 +0100 |
| commit | aeb06d51ea3ff689eea744f38f7c08181171fe5a (patch) | |
| tree | 3fe589e6a5d1d7edce7d49102ad2da9815092ab2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r8a08g045: Check the source of the CPU PLL settings (diff) | |
| download | linux-rng-aeb06d51ea3ff689eea744f38f7c08181171fe5a.tar.xz linux-rng-aeb06d51ea3ff689eea744f38f7c08181171fe5a.zip | |
clk: renesas: r8a779h0: Add FCPVX clock
Add the FCPVX modules clock for Renesas R-Car V4M.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115175927.3714357-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions