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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2019-11-01 13:36:27 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-11-01 13:36:27 +0100 |
| commit | b07e816fc416bba0d00a46c9fc93d1387bf847f6 (patch) | |
| tree | 21a1343b06e7de90267e91b38842578176337c1c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r8a77965: Remove superfluous semicolon (diff) | |
| parent | dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions (diff) | |
| download | linux-rng-b07e816fc416bba0d00a46c9fc93d1387bf847f6.tar.xz linux-rng-b07e816fc416bba0d00a46c9fc93d1387bf847f6.zip | |
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into clk-renesas-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions