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| author |   Rajat Jain <rajatja@google.com> | 2017-01-02 22:34:11 -0800 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2017-02-14 17:43:51 -0600 |
| commit | b2103ccbb67e3ef0f7a75d21c989f9614ddbcaca (patch) | |
| tree | f4690841da7a101ab9ecd4a96e3968ec5c2d017b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | PCI/ASPM: Add L1 substate capability structure register definitions (diff) | |
| download | linux-rng-b2103ccbb67e3ef0f7a75d21c989f9614ddbcaca.tar.xz linux-rng-b2103ccbb67e3ef0f7a75d21c989f9614ddbcaca.zip | |
PCI/ASPM: Add support for L1 substates
Add support for ASPM L1 substates. For details about L1 substates, see the
PCIe r3.1 spec, which includes the ECN below in secs 5.5 and 7.33.
Add macros for the 4 new L1 substates, and add a new ASPM "POWER_SUPERSAVE"
policy that can be used to enable L1 substates on a system if desired. The
new policy is in a sense, a superset of the existing POWERSAVE policy. The
4 policies are now:
DEFAULT: Reads and uses whatever ASPM states BIOS enabled
PERFORMANCE: Everything except L0 disabled.
POWERSAVE: L0s and L1 enabled (but not L1 substates)
POWER_SUPERSAVE: L0s + L1 + L1 substates also enabled
[bhelgaas: add PCIe r3.1 spec reference]
Link: https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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