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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-07-13 10:35:57 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-07-13 10:35:57 +0200 |
| commit | b4a086fead547187313304022f7517fb0c412e89 (patch) | |
| tree | 7536dfd252cb6c087c26608ab4827ec7f371a88f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzg2: Mark RWDT clocks as critical (diff) | |
| parent | clk: renesas: Add r8a774e1 CPG Core Clock Definitions (diff) | |
| download | linux-rng-b4a086fead547187313304022f7517fb0c412e89.tar.xz linux-rng-b4a086fead547187313304022f7517fb0c412e89.zip | |
Merge tag 'renesas-r8a774e1-dt-binding-defs-tag' into clk-renesas-for-v5.9
Renesas RZ/G2H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G2H (R8A774E1)
SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions