KVM: selftests: Add defines for AMD PMU CPUID features and properties

Add macros for AMD's PMU related CPUID features.  To make it easier to
cross reference selftest code with KVM/kernel code, use the same macro
names as the kernel for the features.

For reference, the AMD APM defines the features/properties as:

  * PerfCtrExtCore (six core counters instead of four)
  * PerfCtrExtNB (four counters for northbridge events)
  * PerfCtrExtL2I (four counters for L2 cache events)
  * PerfMonV2 (support for registers to control multiple
    counters with a single register write)
  * LbrAndPmcFreeze (support for freezing last branch recorded stack on
    performance counter overflow)
  * NumPerfCtrCore (number of core counters)
  * NumPerfCtrNB (number of northbridge counters)

Signed-off-by: Colton Lewis <coltonlewis@google.com>
Link: https://lore.kernel.org/r/20240918205319.3517569-3-coltonlewis@google.com
[sean: massage changelog, use same names as the kernel]
Signed-off-by: Sean Christopherson <seanjc@google.com>

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