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| author |   Manasi Navare <manasi.d.navare@intel.com> | 2021-01-22 15:26:43 -0800 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2021-01-25 15:23:18 -0800 |
| commit | c7f0f4372b30e5496bea1a6cfdf94904dee8c0fd (patch) | |
| tree | d3263ba8d3e6b4de6ca77b9bc3f476fb40f2e943 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink (diff) | |
| download | linux-rng-c7f0f4372b30e5496bea1a6cfdf94904dee8c0fd.tar.xz linux-rng-c7f0f4372b30e5496bea1a6cfdf94904dee8c0fd.zip | |
drm/i915/display: Add HW state readout for VRR
This functions gets the VRR config from the VRR registers
to match the crtc state variables for VRR.
v2:
* Rebase (Manasi)
* Use HAS_VRR (Jani N)
v3:
* Get pipeline_full, flipline (Ville)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-14-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions