diff options
| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:14:22 +0200 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2020-06-24 12:14:30 +0200 |
| commit | d4db5721f3c847df43b967d9f02994b15e4a48e6 (patch) | |
| tree | 191118bd24cc0a467a6407b01c4eb97d20e4d53c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: meson: g12a: Add support for NNA CLK source clocks (diff) | |
| download | linux-rng-d4db5721f3c847df43b967d9f02994b15e4a48e6.tar.xz linux-rng-d4db5721f3c847df43b967d9f02994b15e4a48e6.zip | |
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't
know the relation between this clock and RGMII Ethernet. It turns out
that fclk_div2 is used as "timing adjustment clock" to generate the RX
delay on the MAC side - which was enabled by u-boot on Odriod-C1. When
using the RX delay on the PHY side or not using a RX delay at all then
this clock can be disabled.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200620161422.24114-1-martin.blumenstingl@googlemail.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions