diff options
| author |   Florian Fainelli <f.fainelli@gmail.com> | 2017-04-20 12:05:45 -0700 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2017-04-28 15:23:36 +0100 |
| commit | f5337346cd8fe1b105f319b4b7fb06fe25c54480 (patch) | |
| tree | 44a7b3559a6c24f2f7e4dbe731251b0b652e3131 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: module: split core and init PLT sections (diff) | |
| download | linux-rng-f5337346cd8fe1b105f319b4b7fb06fe25c54480.tar.xz linux-rng-f5337346cd8fe1b105f319b4b7fb06fe25c54480.zip | |
arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills
Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions