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author | 2018-09-05 17:33:09 +0800 | |
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committer | 2018-10-15 23:11:14 -0700 | |
commit | 360fe725f8849aaddc53475fef5d4a0c439b05ae (patch) | |
tree | 7402e2f230edc00746bf98dfdfb1cad6dd248b4a /tools/perf/scripts/python/export-to-sqlite.py | |
parent | MIPS: Loongson-3: Fix CPU UART irq delivery problem (diff) | |
download | linux-rng-360fe725f8849aaddc53475fef5d4a0c439b05ae.tar.xz linux-rng-360fe725f8849aaddc53475fef5d4a0c439b05ae.zip |
MIPS: Loongson-3: Fix BRIDGE irq delivery problem
After commit e509bd7da149dc349160 ("genirq: Allow migration of chained
interrupts by installing default action") Loongson-3 fails at here:
setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
This is because both chained_action and cascade_irqaction don't have
IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET
timer interrupt can't be delivered during S3. So we set the irqchip of
the chained irq to loongson_irq_chip which doesn't disable the chained
irq in CP0.Status.
Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20434/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions