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| author |   Luca Weiss <luca.weiss@fairphone.com> | 2025-04-25 14:12:57 +0200 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2025-05-06 13:18:31 -0700 |
| commit | afdfd829a99e467869e3ca1955fb6c6e337c340a (patch) | |
| tree | 947837a9e876435b1d785f54f2dda2f987b515aa /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs (diff) | |
| download | linux-rng-afdfd829a99e467869e3ca1955fb6c6e337c340a.tar.xz linux-rng-afdfd829a99e467869e3ca1955fb6c6e337c340a.zip | |
clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
Compared to the msm-4.19 driver the mainline GDSC driver always sets the
bits for en_rest, en_few & clk_dis, and if those values are not set
per-GDSC in the respective driver then the default value from the GDSC
driver is used. The downstream driver only conditionally sets
clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree.
Correct this situation by explicitly setting those values. For all GDSCs
the reset value of those bits are used.
Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250425-sm6350-gdsc-val-v1-3-1f252d9c5e4e@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions