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authorWolfram Sang <wsa+renesas@sang-engineering.com>2021-03-05 15:32:57 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-03-10 10:48:57 +0100
commitc52f4f839a33b1757aae25af41fc0037645e341c (patch)
treeca795577c8efb17114feb308ebb7838735cea32c /tools/perf/scripts/python/exported-sql-viewer.py
parentclk: renesas: r8a77965: Add DAB clock (diff)
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clk: renesas: r8a779a0: Add TMU clocks
Also add CL16MCK source clock for TMU0. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210305143259.12622-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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