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| author |   John Madieu <john.madieu.xa@bp.renesas.com> | 2025-02-27 13:24:38 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-03-06 16:39:31 +0100 |
| commit | e1a098330ef0555ad216e549a018d99aee7752c1 (patch) | |
| tree | d645c3845a90e5655a3e512ff9f6840f52ca26e6 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 (diff) | |
| download | linux-rng-e1a098330ef0555ad216e549a018d99aee7752c1.tar.xz linux-rng-e1a098330ef0555ad216e549a018d99aee7752c1.zip | |
clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP
Add required clocks and resets signals for the TSU IP available on the
Renesas RZ/G3E SoC
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions