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| author |   Thierry Reding <treding@nvidia.com> | 2016-06-09 17:50:57 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-07-14 16:20:26 +0200 |
| commit | 237d5cc779bc506205420846f74f02c40d63f08e (patch) | |
| tree | 13756fc37b0f0c3befa38bc9c31f9ba86972a0e6 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | arm64: tegra: Add XUSB powergates on Tegra210 (diff) | |
| download | linux-rng-237d5cc779bc506205420846f74f02c40d63f08e.tar.xz linux-rng-237d5cc779bc506205420846f74f02c40d63f08e.zip | |
arm64: tegra: Add sor1_src clock
The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions