linux-rng - Development tree for the kernel CSPRNG

Age	Commit message (Expand)	Author	Files	Lines
2026-08-17	Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile	Stephen Boyd	9	-52/+312
2026-08-17	Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile	Stephen Boyd	1	-0/+1
2026-07-28	clk: mediatek: mt8135: Fix inverted gate control for devapc_ck	Akari Tsuyukusa	1	-1/+4
2026-07-28	clk: mediatek: Add mt8173-mfgtop driver	Chen-Yu Tsai	3	-0/+253
2026-07-28	clk: mediatek: pllfh: Fix IO remapping leak in register_pllfhs error path	Louis-Alexis Eyraud	1	-49/+49
2026-07-28	clk: mediatek: remove unneeded 'fast_io' parameter in regmap_config	Wolfram Sang	1	-1/+0
2026-07-28	clk: mediatek: mt6735-vencsys: add missing MODULE_DEVICE_TABLE()	Pengpeng Hou	1	-0/+1
2026-07-28	clk: mediatek: mt6735-vdecsys: add missing MODULE_DEVICE_TABLE()	Pengpeng Hou	1	-0/+1
2026-07-27	clk: mediatek: mt6735: Unregister PLLs on probe failure	Myeonghun Pak	1	-1/+4
2026-07-03	Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c files)	Uwe Kleine-König (The Capable Hub)	47	-47/+0
2026-06-29	clk: mediatek: mt8196: Select REGMAP_MMIO for vlpckgen	Akari Tsuyukusa	1	-0/+1
2026-04-28	clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes	Daniel Golle	1	-42/+38
2026-04-28	clk: mediatek: mt8192: use MUX_CLR_SET	Daniel Golle	1	-2/+2
2026-04-28	clk: mediatek: add MUX_CLR_SET macro	Daniel Golle	1	-0/+5
2026-02-21	Convert 'alloc_flex' family to use the new default GFP_KERNEL argument	Linus Torvalds	1	-1/+1
2026-02-21	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	Linus Torvalds	7	-9/+9
2026-02-21	treewide: Replace kmalloc with kmalloc_obj for non-scalar types	Kees Cook	7	-10/+10
2026-01-22	clk: mediatek: Fix error handling in runtime PM setup	Haotian Zhang	1	-5/+7
2026-01-22	clk: mediatek: don't select clk-mt8192 for all ARM64 builds	Bartosz Golaszewski	1	-1/+1
2026-01-22	clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks	Nicolas Frattaroli	3	-6/+11
2026-01-22	clk: mediatek: Refactor pllfh registration to pass device	Nicolas Frattaroli	7	-17/+20
2026-01-22	clk: mediatek: Pass device to clk_hw_register for PLLs	Nicolas Frattaroli	3	-5/+10
2026-01-22	clk: mediatek: Refactor pll registration to pass device	Nicolas Frattaroli	24	-32/+34
2026-01-22	clk: mediatek: Drop __initconst from gates	Sjoerd Simons	2	-4/+4
2025-10-06	Merge branch 'clk-determine-rate' into clk-next	Stephen Boyd	3	-9/+11
2025-09-21	clk: mediatek: Add MT8196 vencsys clock support	Laura Nao	3	-0/+244
2025-09-21	clk: mediatek: Add MT8196 vdecsys clock support	Laura Nao	3	-0/+261
2025-09-21	clk: mediatek: Add MT8196 ovl1 clock support	Laura Nao	2	-1/+155
2025-09-21	clk: mediatek: Add MT8196 ovl0 clock support	Laura Nao	2	-1/+156
2025-09-21	clk: mediatek: Add MT8196 disp-ao clock support	Laura Nao	2	-1/+81
2025-09-21	clk: mediatek: Add MT8196 disp1 clock support	Laura Nao	2	-1/+171
2025-09-21	clk: mediatek: Add MT8196 disp0 clock support	Laura Nao	3	-0/+178
2025-09-21	clk: mediatek: Add MT8196 mfg clock support	Laura Nao	3	-0/+158
2025-09-21	clk: mediatek: Add MT8196 mdpsys clock support	Laura Nao	3	-0/+194
2025-09-21	clk: mediatek: Add MT8196 mcu clock support	Laura Nao	3	-0/+175
2025-09-21	clk: mediatek: Add MT8196 I2C clock support	Laura Nao	3	-0/+126
2025-09-21	clk: mediatek: Add MT8196 pextpsys clock support	Laura Nao	3	-0/+139
2025-09-21	clk: mediatek: Add MT8196 ufssys clock support	Laura Nao	3	-0/+116
2025-09-21	clk: mediatek: Add MT8196 peripheral clock support	Laura Nao	2	-1/+144
2025-09-21	clk: mediatek: Add MT8196 vlpckgen clock support	Laura Nao	2	-1/+726
2025-09-21	clk: mediatek: Add MT8196 topckgen2 clock support	Laura Nao	2	-1/+570
2025-09-21	clk: mediatek: Add MT8196 topckgen clock support	Laura Nao	2	-1/+986
2025-09-21	clk: mediatek: Add MT8196 apmixedsys clock support	Laura Nao	3	-0/+213
2025-09-21	clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro	Laura Nao	1	-0/+19
2025-09-21	clk: mediatek: clk-gate: Add ops for gates with HW voter	Laura Nao	2	-3/+71
2025-09-21	clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct	Laura Nao	1	-33/+19
2025-09-21	clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC	Laura Nao	3	-1/+114
2025-09-21	clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()	Laura Nao	2	-0/+17
2025-09-21	clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC	Laura Nao	2	-0/+94
2025-09-21	clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC	Laura Nao	2	-1/+44