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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-05-07drm/amdgpu: Add documentation to some parts of the AMDGPU ring and wbRodrigo Siqueira1-0/+74
2025-04-08drm/amdgpu: add ring flag for no user submissionsAlex Deucher1-1/+1
2025-04-08drm/amdgpu: remove is_mes_queue flagAlex Deucher1-14/+0
2025-03-21drm/amd/amdgpu: Increase max rings to enable SDMA page ringJesse.zhang@amd.com1-1/+1
2025-02-25drm/amdgpu: increase AMDGPU_MAX_RINGSTao Zhou1-1/+1
2025-02-25drm/amdgpu: Introduce cached_rptr and is_guilty callback in amdgpu_ringJesse.zhang@amd.com1-0/+3
2025-02-17drm/amdgpu: add RAS CPER ring bufferTao Zhou1-0/+1
2025-02-12drm/amdgpu: increase amdgpu max rings limitSathishkumar S1-1/+1
2024-12-18drm/amdgpu: drop the amdgpu_device argument from amdgpu_ib_freePierre-Eric Pelloux-Prayer1-2/+1
2024-10-28drm/amdgpu: drop volatile from ring bufferChristian König1-7/+4
2024-10-08drm/amdgpu: no need to log error in multi ring writeSunil Khatri1-3/+0
2024-10-08drm/amdgpu: move error log from ring write to commitSunil Khatri1-2/+0
2024-08-16drm/amdgpu: Emit cleaner shader at end of IB submissionAlex Deucher1-0/+1
2024-08-16drm/amdgpu: add new ring reset callbackAlex Deucher1-0/+2
2024-03-04drm/amdgpu: workaround to avoid SET_Q_MODE packets v2Christian König1-0/+3
2024-03-04drm/amdgpu: cleanup conditional executionChristian König1-4/+26
2024-01-31drm/amdgpu: Fix the warning info in mode1 resetMa Jun1-1/+1
2023-08-31drm/amdgpu: add UMSCH RING TYPE definitionLang Yu1-1/+2
2023-08-31drm/amdgpu: add VPE RING TYPE definitionHuang Rui1-0/+2
2023-08-09drm/amdgpu: Clean up errors in amdgpu_ring.hRan Sun1-1/+1
2023-06-15drm/amdgpu: add amdgpu_error_* debugfs fileChristian König1-0/+1
2023-06-09drm/amdgpu: Modify indirect buffer packages for resubmissionJiadong Zhu1-0/+9
2023-06-09drm/amdgpu: add partition ID track in ringJames Zhu1-0/+1
2023-06-09drm/amdgpu: increase AMDGPU_MAX_RINGSLe Ma1-1/+1
2023-06-09drm/amdgpu: increase AMDGPU_MAX_HWIP_RINGSJames Zhu1-1/+1
2023-06-09drm/amdgpu: increase MAX setting to hold more jpeg instancesJames Zhu1-1/+1
2023-06-09drm/amdgpu: adjust some basic elements for multiple AID caseLe Ma1-2/+2
2023-04-24drm/amdgpu: track MQD size for gfx and computeAlex Deucher1-0/+1
2023-04-24drm/amdgpu: add gfx shadow CS IOCTL supportChristian König1-0/+3
2023-04-18drm/amdgpu: Add a max ibs per submission limit.Bas Nieuwenhuizen1-0/+1
2023-04-14drm/amdgpu: add some basic elements for multiple XCD caseLe Ma1-0/+1
2023-04-14drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4)Le Ma1-1/+1
2023-03-14Merge tag 'drm-misc-next-2023-03-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-nextDave Airlie1-1/+2
2023-03-01drm/amd: Convert amdgpu to use suballocation helper.Maarten Lankhorst1-1/+2
2023-02-08amd/amdgpu: remove test ib on hw ringJesseZhang1-1/+1
2022-12-02drm/amdgpu: MCBP based on DRM scheduler (v9)Jiadong.Zhu1-0/+8
2022-12-02drm/amdgpu: Modify unmap_queue format for gfx9 (v6)Jiadong.Zhu1-0/+1
2022-12-02drm/amdgpu: Add software ring callbacks for gfx9 (v8)Jiadong.Zhu1-0/+1
2022-12-02drm/amdgpu: Introduce gfx software ring (v9)Jiadong.Zhu1-0/+4
2022-06-28drm/amdgpu: Prevent race between late signaled fences and GPU reset.Andrey Grodzovsky1-0/+1
2022-05-04drm/amdgpu: define ring structure to access rptr/wptr/fenceJack Xiao1-0/+6
2022-05-04drm/amdgpu: add mes ctx data in amdgpu_ringJack Xiao1-0/+5
2022-05-04drm/amdgpu: add the per-context meta data v3Jack Xiao1-0/+9
2022-05-04drm/amdgpu: add helper function to initialize mqd from ring v4Jack Xiao1-0/+2
2022-03-31drm/amdgpu: Sync up header and implementation to use the same parameter namesMa Jun1-2/+2
2022-03-15drm/amdgpu: only allow secure submission on rings which support thatLang Yu1-0/+1
2022-03-04drm/amdgpu: use job and ib structures directly in CS parsersChristian König1-4/+19
2022-03-04drm/amdgpu: header cleanupChristian König1-5/+30
2022-02-09drm/amdgpu: Move scheduler init to after XGMI is readyAndrey Grodzovsky1-3/+3
2021-12-17drm/amdgpu: introduce new amdgpu_fence object to indicate the job embedded fenceHuang Rui1-3/+1
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