aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_gvt_mmio_table.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-04-25drm/i915/vga: Extract intel_vga_regs.hVille Syrjälä1-0/+1
2025-02-27drm/i915/pfit: split out intel_pfit_regs.hJani Nikula1-0/+1
2025-01-23drm/i915: fix typos in drm/i915 filesNitin Gote1-1/+1
2024-12-16drm/i915: split out i9xx_wm_regs.hJani Nikula1-0/+1
2024-12-11Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-1/+1
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra1-1/+1
2024-11-11drm/i915/crt: Extract intel_crt_regs.hVille Syrjälä1-0/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N2Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M2Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N1Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M1Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N2Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M2Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N1Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M1Jani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4XJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4XJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPESTATJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPEDSLJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANSCONFJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MULTJani Nikula1-3/+3
2024-06-07drm/i915: pass dev_priv explicitly to PIPESRCJani Nikula1-3/+3
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFTJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to BCLRPATJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VSYNCJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VBLANKJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VTOTALJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HSYNCJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HBLANKJani Nikula1-4/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HTOTALJani Nikula1-4/+4
2024-05-31drm/i915/gvt: use proper macros for DP AUX CH CTL registersJani Nikula1-4/+4
2024-05-28drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GCPJani Nikula1-3/+3
2024-05-28drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_CTLJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPSURFLIVEJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPOFFSETJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPSURFJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPSIZEJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPPOSJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPSTRIDEJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPADDRJani Nikula1-3/+3
2024-05-24drm/i915: pass dev_priv explicitly to DSPCNTRJani Nikula1-3/+3
2024-05-22drm/i915: Extract i9xx_plane_regs.hVille Syrjälä1-0/+1
2024-05-16drm/i915: pass dev_priv explicitly to CUR_FBC_CTLJani Nikula1-3/+3
2024-05-16drm/i915: pass dev_priv explicitly to CURPOSJani Nikula1-3/+3
2024-05-16drm/i915: pass dev_priv explicitly to CURBASEJani Nikula1-3/+3
2024-05-16drm/i915: pass dev_priv explicitly to CURCNTRJani Nikula1-3/+3
2024-05-15drm/i915/gvt: Use PLANE_CTL and PLANE_SURF definesVille Syrjälä1-6/+6
2024-05-15drm/i915/gvt: Use the full PLANE_KEY*() definesVille Syrjälä1-9/+9
2024-05-15drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() defineVille Syrjälä1-12/+12
2024-05-15drm/i915/gvt: Use the proper PLANE_AUX_DIST() defineVille Syrjälä1-12/+12
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.