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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT8195 series HDMI-TX Encoder
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- CK Hu <ck.hu@mediatek.com>
description:
The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on
the HDMI Specification 2.0b.
properties:
compatible:
enum:
- mediatek,mt8188-hdmi-tx
- mediatek,mt8195-hdmi-tx
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: HDMI Peripheral Bus (APB) clock
- description: HDCP and HDMI_TOP clock
- description: HDCP, HDMI_TOP and HDMI Audio reference clock
- description: VPP HDMI Split clock
clock-names:
items:
- const: bus
- const: hdcp
- const: hdcp24m
- const: hdmi-split
i2c:
type: object
$ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
unevaluatedProperties: false
description: HDMI DDC I2C controller
phys:
maxItems: 1
description: PHY providing clocking TMDS and pixel to controller
phy-names:
items:
- const: hdmi
power-domains:
maxItems: 1
'#sound-dai-cells':
const: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Input port, usually connected to the output port of a DPI
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port that must be connected either to the input port of
a HDMI connector node containing a ddc-i2c-bus, or to the input
port of an attached bridge chip, such as a SlimPort transmitter.
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- phys
- phy-names
- ports
allOf:
- $ref: /schemas/sound/dai-common.yaml#
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt8195-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
hdmi@1c300000 {
compatible = "mediatek,mt8195-hdmi-tx";
reg = <0 0x1c300000 0 0x1000>;
clocks = <&topckgen CLK_TOP_HDMI_APB>,
<&topckgen CLK_TOP_HDCP>,
<&topckgen CLK_TOP_HDCP_24M>,
<&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&hdmi_phy>;
phy-names = "hdmi";
power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
#sound-dai-cells = <1>;
hdmitx_ddc: i2c {
compatible = "mediatek,mt8195-hdmi-ddc";
clocks = <&clk26m>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
hdmi_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
|
