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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: V3 Semiconductor V360 EPC PCI bridge
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
This bridge is found in the ARM Integrator/AP (Application Platform)
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
items:
- const: arm,integrator-ap-pci
- const: v3,v360epc-pci
reg:
items:
- description: V3 host bridge controller
- description: Configuration space
clocks:
maxItems: 1
dma-ranges:
maxItems: 2
description:
The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB,
4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The
memory should be marked as pre-fetchable.
interrupts:
description: Bus Error IRQ
maxItems: 1
ranges:
description:
The non-prefetchable and prefetchable memory windows must each be exactly
256MB (0x10000000) in size. The prefetchable memory window must be
immediately adjacent to the non-prefetchable memory window.
required:
- compatible
- reg
- clocks
- dma-ranges
- "#interrupt-cells"
- interrupt-map
- interrupt-map-mask
unevaluatedProperties: false
examples:
- |
pci@62000000 {
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
device_type = "pci";
interrupt-parent = <&pic>;
interrupts = <17>; /* Bus error IRQ */
clocks = <&pciclk>;
ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>, /* 16 MiB @ LB 60000000 */
<0x02000000 0 0x40000000 0x40000000 0 0x10000000>, /* 256 MiB @ LB 40000000 1:1 */
<0x42000000 0 0x50000000 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */
<0x02000000 0 0x80000000 0x80000000 0 0x40000000>; /* CM alias: 1GB @ LB 80000000 */
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map =
/* IDSEL 9 */
<0x4800 0 0 1 &pic 13>, /* INT A on slot 9 is irq 13 */
<0x4800 0 0 2 &pic 14>, /* INT B on slot 9 is irq 14 */
<0x4800 0 0 3 &pic 15>, /* INT C on slot 9 is irq 15 */
<0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */
/* IDSEL 10 */
<0x5000 0 0 1 &pic 14>, /* INT A on slot 10 is irq 14 */
<0x5000 0 0 2 &pic 15>, /* INT B on slot 10 is irq 15 */
<0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */
<0x5000 0 0 4 &pic 13>, /* INT D on slot 10 is irq 13 */
/* IDSEL 11 */
<0x5800 0 0 1 &pic 15>, /* INT A on slot 11 is irq 15 */
<0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */
<0x5800 0 0 3 &pic 13>, /* INT C on slot 11 is irq 13 */
<0x5800 0 0 4 &pic 14>, /* INT D on slot 11 is irq 14 */
/* IDSEL 12 */
<0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */
<0x6000 0 0 2 &pic 13>, /* INT B on slot 12 is irq 13 */
<0x6000 0 0 3 &pic 14>, /* INT C on slot 12 is irq 14 */
<0x6000 0 0 4 &pic 15>; /* INT D on slot 12 is irq 15 */
};
...
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