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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-16 15:32:34 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-16 19:42:19 +0100 |
| commit | 972c646f1cfed31ec9661ee7abc161b3ccf21fdd (patch) | |
| tree | f800925a17bdf55a28fe579312bd7f79963cfcfa /drivers/gpu/drm/i915/i915_gem_gtt.h | |
| parent | drm/i915: Store i915_ggtt as the backpointer on fence registers (diff) | |
| download | linux-stable-972c646f1cfed31ec9661ee7abc161b3ccf21fdd.tar.xz linux-stable-972c646f1cfed31ec9661ee7abc161b3ccf21fdd.zip | |
drm/i915: Move swizzle_bit under i915_ggtt
The HW performs swizzling as part of its fence tiling inside the Global
GTT. We already do the probing of the HW settings from the GGTT setup,
complete the picture by storing the information as part of the GGTT. The
primary benefit is the consistency of our probe routines do not break
the i915_ggtt encapsulation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191016143234.4075-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 0a18fdfe63ff..f074f1de66e8 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -411,6 +411,11 @@ struct i915_ggtt { int mtrr; + /** Bit 6 swizzling required for X tiling */ + u32 bit_6_swizzle_x; + /** Bit 6 swizzling required for Y tiling */ + u32 bit_6_swizzle_y; + u32 pin_bias; unsigned int num_fences; |