diff options
| author |   Jerome Brunet <jbrunet@baylibre.com> | 2019-12-18 18:24:17 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2019-12-18 20:00:24 +0000 |
| commit | 864cee90d4bd870e5d5e5a0b1a6f055f4f951350 (patch) | |
| tree | 42cfa457b0447147fecaed5e1c2cddc15dc33f2e /sound/soc/meson/axg-fifo.h | |
| parent | ASoC: topology: Prevent use-after-free in snd_soc_get_pcm_runtime() (diff) | |
| download | linux-stable-864cee90d4bd870e5d5e5a0b1a6f055f4f951350.tar.xz linux-stable-864cee90d4bd870e5d5e5a0b1a6f055f4f951350.zip | |
ASoC: meson: axg-fifo: fix fifo threshold setup
On TODDR sm1, the fifo threshold register field is slightly different
compared to the other SoCs. This leads to the fifo A being flushed to
memory every 8kB. If the period is smaller than that, several periods
are pushed to memory and notified at once. This is not ideal.
Fix the register field update. With this, the fifos are flushed every
128B. We could still do better, like adapt the threshold depending on
the period size, but at least it consistent across the different
SoC/fifos
Fixes: 5ac825c3d85e ("ASoC: meson: axg-toddr: add sm1 support")
Reported-by: Alden DSouza <aldend@google.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20191218172420.1199117-2-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/meson/axg-fifo.h')
| -rw-r--r-- | sound/soc/meson/axg-fifo.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h index cf928d43b558..c442195ba191 100644 --- a/sound/soc/meson/axg-fifo.h +++ b/sound/soc/meson/axg-fifo.h @@ -9,7 +9,9 @@ struct clk; struct platform_device; +struct reg_field; struct regmap; +struct regmap_field; struct reset_control; struct snd_soc_component_driver; @@ -50,8 +52,6 @@ struct snd_soc_pcm_runtime; #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) #define CTRL1_STATUS2_SEL(x) ((x) << 8) #define STATUS2_SEL_DDR_READ 0 -#define CTRL1_THRESHOLD_MASK GENMASK(23, 16) -#define CTRL1_THRESHOLD(x) ((x) << 16) #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) #define CTRL1_FRDDR_DEPTH(x) ((x) << 24) #define FIFO_START_ADDR 0x08 @@ -67,12 +67,14 @@ struct axg_fifo { struct regmap *map; struct clk *pclk; struct reset_control *arb; + struct regmap_field *field_threshold; int irq; }; struct axg_fifo_match_data { const struct snd_soc_component_driver *component_drv; struct snd_soc_dai_driver *dai_drv; + struct reg_field field_threshold; }; int axg_fifo_pcm_open(struct snd_soc_component *component, |