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authorStafford Horne <shorne@gmail.com>2022-05-11 21:05:41 +0900
committerJason A. Donenfeld <Jason@zx2c4.com>2022-05-11 14:56:02 +0200
commitda174ceda30b802cc8b1ece2ecb86e941afe3530 (patch)
tree310e22378faf1728d8f08fc5186b0217359f8181
parenthw/openrisc: use right OMPIC size variable (diff)
downloadqemu-openrisc-da174ceda30b802cc8b1ece2ecb86e941afe3530.tar.xz
qemu-openrisc-da174ceda30b802cc8b1ece2ecb86e941afe3530.zip
target/openrisc: Do not reset delay slot flag on early tb exitHEADmaster
This was found when running linux crypto algorithm selftests used by wireguard. We found that randomly the tests would fail. We found through investigation that a combination of a tick timer interrupt, raised when executing a delay slot instruction at a page boundary caused the issue. This was caused when handling the TB_EXIT_REQUESTED case in cpu_tb_exec. On OpenRISC, which doesn't implement synchronize_from_tb, set_pc was being used as a fallback. The OpenRISC set_pc implementation clears dflag, which caused the exception handling logic to not account for the delay slot. This was the bug, because it meant when execution resumed after the interrupt was handling it resumed in the wrong place. Fix this by implementing synchronize_from_tb which simply updates pc, and not clear the delay slot flag. Reported-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
-rw-r--r--target/openrisc/cpu.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index dfbafc5236..41d1b2a24a 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "exec/exec-all.h"
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -30,6 +31,15 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.dflag = 0;
}
+static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ cpu->env.pc = tb->pc;
+}
+
+
static bool openrisc_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD |
@@ -186,6 +196,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
+ .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
#ifndef CONFIG_USER_ONLY
.tlb_fill = openrisc_cpu_tlb_fill,