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| author |   Peter Maydell <peter.maydell@linaro.org> | 2024-02-06 13:29:28 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-02-15 14:32:39 +0000 |
| commit | a71e26461464fc50ef84279dc7fceb40960182c1 (patch) | |
| tree | ef0217ce020d6716d92d5f10305c6a889c4bf71e /docs/conf.py | |
| parent | hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM (diff) | |
| download | qemu-a71e26461464fc50ef84279dc7fceb40960182c1.tar.xz qemu-a71e26461464fc50ef84279dc7fceb40960182c1.zip | |
hw/arm/mps3r: Add UARTs
This board has a lot of UARTs: there is one UART per CPU in the
per-CPU peripheral part of the address map, whose interrupts are
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
normal part of the peripheral space, whose interrupts are shared
peripheral interrupts.
Connect and wire them all up; this involves some OR gates where
multiple overflow interrupts are wired into one GIC input.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
Diffstat (limited to 'docs/conf.py')
0 files changed, 0 insertions, 0 deletions