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| author |   Max Filippov <jcmvbkbc@gmail.com> | 2022-04-24 08:33:16 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-05-06 15:27:40 -0700 |
| commit | 8164f14bb98dce986b755af4b3dfee3eb99c95a1 (patch) | |
| tree | e9d62c489142251f203cbe16780b1c061c2aeb96 /linux-user/syscall.c | |
| parent | tests/tcg/xtensa: fix build for cores without windowed registers (diff) | |
| download | qemu-8164f14bb98dce986b755af4b3dfee3eb99c95a1.tar.xz qemu-8164f14bb98dce986b755af4b3dfee3eb99c95a1.zip | |
tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent
tests that expect to raise an exception. Restore vecbase SR to its
reset value after the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'linux-user/syscall.c')
0 files changed, 0 insertions, 0 deletions