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authorAlexander Monakov <amonakov@ispras.ru>2024-02-06 23:48:04 +0300
committerRichard Henderson <richard.henderson@linaro.org>2024-05-03 08:03:04 -0700
commit8a917b99d5394d34ffcd851c8b287ced6eb48133 (patch)
treee0f51fdca77a1724f3cf22e3f5acba93d7aee190 /scripts/coverage/compare_gcov_json.py
parentMerge tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu into staging (diff)
downloadqemu-8a917b99d5394d34ffcd851c8b287ced6eb48133.tar.xz
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util/bufferiszero: Remove SSE4.1 variant
The SSE4.1 variant is virtually identical to the SSE2 variant, except for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing if an SSE register is all zeroes. The PTEST instruction decodes to two uops, so it can be handled only by the complex decoder, and since CMP+JNE are macro-fused, both sequences decode to three uops. The uops comprising the PTEST instruction dispatch to p0 and p5 on Intel CPUs, so PCMPEQB+PMOVMSKB is comparatively more flexible from dispatch standpoint. Hence, the use of PTEST brings no benefit from throughput standpoint. Its latency is not important, since it feeds only a conditional jump, which terminates the dependency chain. I never observed PTEST variants to be faster on real hardware. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-2-amonakov@ispras.ru>
Diffstat (limited to 'scripts/coverage/compare_gcov_json.py')
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