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author | 2024-05-02 09:55:24 -0700 | |
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committer | 2024-05-05 21:02:48 +0100 | |
commit | 9157dccc7e71f7c94581c38f38acbef9a21bbe9a (patch) | |
tree | 85aa5a01a7840388929584f7d9e40c2caed2a981 /scripts/coverage/compare_gcov_json.py | |
parent | target/sparc: Fix FEXPAND (diff) | |
download | qemu-9157dccc7e71f7c94581c38f38acbef9a21bbe9a.tar.xz qemu-9157dccc7e71f7c94581c38f38acbef9a21bbe9a.zip |
target/sparc: Fix FMUL8x16
This instruction has f32 as source1, which alters the
decoding of the register number, which means we've been
passing the wrong data for odd register numbers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-4-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'scripts/coverage/compare_gcov_json.py')
0 files changed, 0 insertions, 0 deletions