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| author |   Peter Maydell <peter.maydell@linaro.org> | 2023-03-14 14:28:47 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-03-14 14:28:47 +0000 |
| commit | caaf72fe471e1a1e4c7c2b93d29726267b49383b (patch) | |
| tree | 32086404f463cd404639a9561bcb2ec64e5ed471 /scripts/coverage/compare_gcov_json.py | |
| parent | Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (diff) | |
| parent | Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (diff) | |
| download | qemu-caaf72fe471e1a1e4c7c2b93d29726267b49383b.tar.xz qemu-caaf72fe471e1a1e4c7c2b93d29726267b49383b.zip | |
Merge tag 'pull-riscv-to-apply-20230314' of https://github.com/alistair23/qemu into staging
Seventh RISC-V PR for 8.0
* Fix slli_uw decoding
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
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# gpg: Signature made Tue 14 Mar 2023 06:37:50 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
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* tag 'pull-riscv-to-apply-20230314' of https://github.com/alistair23/qemu:
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
disas/riscv: Fix slli_uw decoding
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/coverage/compare_gcov_json.py')
0 files changed, 0 insertions, 0 deletions