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author | 2024-04-18 16:20:03 +0100 | |
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committer | 2024-04-30 15:01:07 +0100 | |
commit | f7ddd7b6a1f90cae677303e96b91e866a1570f6a (patch) | |
tree | 305a47052871f43ba3d8cc19cd4fd60699a78fc9 /scripts/coverage/compare_gcov_json.py | |
parent | target/arm: Enable FEAT_ETS2 for -cpu max (diff) | |
download | qemu-f7ddd7b6a1f90cae677303e96b91e866a1570f6a.tar.xz qemu-f7ddd7b6a1f90cae677303e96b91e866a1570f6a.zip |
target/arm: Implement ID_AA64MMFR3_EL1
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for
ID_AA64MMFR3_EL1. Implement this register, so that we can set the
fields if we need to. There's no behaviour change here since we
don't currently set the register value to non-zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
Diffstat (limited to 'scripts/coverage/compare_gcov_json.py')
0 files changed, 0 insertions, 0 deletions