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| author |   Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:06 +0000 |
| commit | 34222fb8101298ead0e43766340843b469597580 (patch) | |
| tree | 8af1e731cf56afb37c46b7236964b287a3924d23 /scripts/qapi-commands.py | |
| parent | target-arm: A64: Implement MSR (immediate) instructions (diff) | |
| download | qemu-34222fb8101298ead0e43766340843b469597580.tar.xz qemu-34222fb8101298ead0e43766340843b469597580.zip | |
target-arm: Implement AArch64 view of CPACR
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole register this way.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'scripts/qapi-commands.py')
0 files changed, 0 insertions, 0 deletions