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| author |   Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2017-02-10 16:25:52 +1100 |
|---|---|---|
| committer |   David Gibson <david@gibson.dropbear.id.au> | 2017-02-22 11:28:28 +1100 |
| commit | 7659ca1a3e22aa298022b1ecb21bf3650a01e814 (patch) | |
| tree | d40f772f16fa9700f6e024a9caf6a7b8595738ce /scripts/qapi-commands.py | |
| parent | target-ppc: Add xscvqpudz and xscvqpuwz instructions (diff) | |
| download | qemu-7659ca1a3e22aa298022b1ecb21bf3650a01e814.tar.xz qemu-7659ca1a3e22aa298022b1ecb21bf3650a01e814.zip | |
target/ppc: Fix LPCR DPFD mask define
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'scripts/qapi-commands.py')
0 files changed, 0 insertions, 0 deletions