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| author |   Kwok Cheung Yeung <kcy@codesourcery.com> | 2013-05-17 14:51:20 -0700 |
|---|---|---|
| committer |   Aurelien Jarno <aurelien@aurel32.net> | 2013-05-20 18:16:17 +0200 |
| commit | ea3164aafccdfdd8a9543787cdfa25fac30a5def (patch) | |
| tree | 9f6c648b8eb0e608f4c3b20e69384fad9c73fa34 /scripts/qapi.py | |
| parent | target-mips: clean-up in BIT_INSV (diff) | |
| download | qemu-ea3164aafccdfdd8a9543787cdfa25fac30a5def.tar.xz qemu-ea3164aafccdfdd8a9543787cdfa25fac30a5def.zip | |
linux-user: Fix MIPS ISA transitions during signal handling
Processors supporting the MIPS16 or microMIPS ISAs set bit 0 in target
addresses to indicate that the target is written using a compressed ISA.
During signal handling, when jumping to or returning from a signal
handler, bit 0 of the destination PC is inspected and MIPS_HFLAG_M16 in
hflags cleared or set accordingly. Bit 0 of the PC is then cleared.
Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'scripts/qapi.py')
0 files changed, 0 insertions, 0 deletions