diff options
| author |   Dongxue Zhang <elta.era@gmail.com> | 2014-07-29 21:48:10 +0800 |
|---|---|---|
| committer |   Leon Alrae <leon.alrae@imgtec.com> | 2014-10-14 13:29:14 +0100 |
| commit | a83bddd60de0dfdbc04c6683c2701682073af5cf (patch) | |
| tree | 725f1149424e69ff01677bc8d372cacaf6822e39 /target-openrisc/exception.c | |
| parent | target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA (diff) | |
| download | qemu-a83bddd60de0dfdbc04c6683c2701682073af5cf.tar.xz qemu-a83bddd60de0dfdbc04c6683c2701682073af5cf.zip | |
target-mips/translate.c: Update OPC_SYNCI
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com: update microMIPS SYNCI as well]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-openrisc/exception.c')
0 files changed, 0 insertions, 0 deletions