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* riscv/disas: Fix disas output of upper immediatesChristoph Müllner2023-07-192-3/+18
* riscv: Add support for the Zfa extensionChristoph Müllner2023-07-102-0/+142
* target/riscv: Add disas support for BF16 extensionsWeiwei Li2023-07-101-0/+44
* disas/riscv: Add support for XThead* instructionsChristoph Müllner2023-07-105-0/+817
* disas/riscv: Add support for XVentanaCondOpsChristoph Müllner2023-07-104-1/+67
* disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner2023-07-101-2/+26
* disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner2023-07-102-17/+25
* disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner2023-07-102-1/+5
* disas/riscv: Move types/constants to new header fileChristoph Müllner2023-07-102-269/+283
* meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé2023-06-201-1/+1
* disas/riscv.c: Remove redundant parenthesesWeiwei Li2023-06-131-109/+110
* disas/riscv.c: Fix lines with over 80 charactersWeiwei Li2023-06-131-61/+140
* disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li2023-06-131-370/+370
* disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li2023-06-131-4/+12
* disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li2023-06-131-1/+7
* target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li2023-06-131-3/+7
* disas/riscv: Decode czero.{eqz,nez}Richard Henderson2023-05-251-0/+6
* disas: Move disas.c into the target-independent source setThomas Huth2023-05-112-7/+8
* disas: Move softmmu specific code to separate fileThomas Huth2023-05-114-70/+93
* disas: Remove target-specific headersRichard Henderson2023-05-111-1/+2
* disas: Remove target_ulong from the interfaceRichard Henderson2023-05-111-10/+9
* disas: Move disas.c to disas/Richard Henderson2023-05-112-1/+402
* disas/riscv.c: add disasm support for Zc*Weiwei Li2023-05-051-1/+227
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin2023-03-141-9/+10
* disas/riscv: Fix slli_uw decodingIvan Klokov2023-03-141-4/+4
* disas/riscv Fix ctzw disassembleIvan Klokov2023-03-051-1/+1
* target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich2023-02-071-4/+4
* mips: Always include nanomips disassemblerPaolo Bonzini2023-01-131-2/+1
* disas/nanomips: Tidy read for 48-bit opcodesRichard Henderson2022-11-081-6/+6
* disas/nanomips: Split out read_u16Richard Henderson2022-11-081-29/+19
* disas/nanomips: Merge insn{1,2,3} into words[3]Richard Henderson2022-11-081-23/+21
* disas/nanomips: Move setjmp into nanomips_disRichard Henderson2022-11-081-25/+17
* disas/nanomips: Remove headers already included by "qemu/osdep.h"Philippe Mathieu-Daudé2022-11-081-4/+0
* disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formatsPhilippe Mathieu-Daudé2022-11-081-1/+1
* disas/nanomips: Fix invalid PRIx64 format calling img_format()Philippe Mathieu-Daudé2022-11-081-1/+2
* disas/nanomips: Fix invalid PRId64 format calling img_format()Philippe Mathieu-Daudé2022-11-081-15/+20
* disas/mips: Fix branch displacement for BEQZC and BNEZCDavid Daney2022-10-311-2/+10
* disas/nanomips: Rename nanomips.cpp to nanomips.cMilica Lazarevic2022-10-312-1/+1
* disas/nanomips: Remove argument passing by refMilica Lazarevic2022-10-311-3/+3
* disas/nanomips: Replace Cpp enums for C enumsMilica Lazarevic2022-10-311-4/+4
* disas/nanomips: Replace exception handlingMilica Lazarevic2022-10-311-55/+45
* disas/nanomips: Expand Dis_info structMilica Lazarevic2022-10-311-1351/+1357
* disas/nanomips: Remove function overloadingMilica Lazarevic2022-10-311-7/+1
* disas/nanomips: Prevent memory leakingMilica Lazarevic2022-10-311-45/+51
* disas/nanomips: Remove CPR functionMilica Lazarevic2022-10-311-65/+45
* disas/nanomips: Remove IMMEDIATE functionsMilica Lazarevic2022-10-311-491/+265
* disas/nanomips: Replace std::string typeMilica Lazarevic2022-10-311-2439/+2337
* disas/nanomips: Delete wrapper functionsMilica Lazarevic2022-10-311-16/+2
* disas/nanomips: Delete copy functionsMilica Lazarevic2022-10-311-1592/+1559
* disas/nanomips: Remove #include <sstream>Milica Lazarevic2022-10-311-1/+0
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