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* hw/riscv/boot.c: Support 64-bit address for initrdCheng Yang2024-06-031-2/+2
* hw: riscv: Allow large kernels to boot by moving the initrd further away in RAMAlexandre Ghiti2024-03-081-6/+6
* target/riscv: Move misa_mxl_max to classAkihiko Odaki2024-02-091-1/+2
* target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza2023-11-071-1/+1
* hw/riscv/boot.c: make riscv_load_initrd() staticDaniel Henrique Barboza2023-02-161-40/+40
* hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-0/+11
* hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-3/+17
* hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza2023-02-071-12/+23
* hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza2023-02-071-5/+25
* hw/riscv/boot.c: calculate fdt size after fdt_pack()Daniel Henrique Barboza2023-02-071-4/+6
* hw/riscv: boot: Don't use CSRs if they are disabledAlistair Francis2023-02-071-0/+9
* hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-201-1/+2
* hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza2023-01-201-2/+4
* hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza2023-01-201-6/+12
* hw/riscv/boot.c: exit early if filename is NULL in load functionsDaniel Henrique Barboza2023-01-201-0/+6
* hw/riscv/boot.c: Introduce riscv_find_firmware()Bin Meng2023-01-201-14/+25
* hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza2023-01-201-0/+9
* hw/riscv/boot.c: make riscv_find_firmware() staticDaniel Henrique Barboza2023-01-201-22/+22
* riscv: re-randomize rng-seed on rebootJason A. Donenfeld2022-10-271-0/+3
* hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L2022-10-141-0/+29
* hw/riscv: Update comment for qtest check in riscv_find_firmware()Bin Meng2022-10-141-2/+2
* hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza2022-09-071-3/+1
* hw/riscv: boot: Reduce FDT address alignment constraintsAlistair Francis2022-07-031-2/+2
* hw/core/loader: return image sizes as ssize_tJamie Iles2022-06-101-2/+3
* hw/riscv: boot: Support 64bit fdt address.Dylan Jhong2022-04-221-5/+7
* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-211-1/+15
* hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke2021-12-201-3/+10
* hw/riscv: boot: Add a PLIC config string functionAlistair Francis2021-10-281-0/+25
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-221-1/+1
* hw/riscv/boot: Check the error of fdt_pack()Alistair Francis2021-07-151-2/+4
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-6/+4
* RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra2021-01-161-4/+4
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-171-21/+10
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-171-25/+30
* hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis2020-12-171-1/+11
* vl: extract softmmu/datadir.cPaolo Bonzini2020-12-101-0/+1
* riscv: do not use ram_size globalPaolo Bonzini2020-12-101-2/+3
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-5/+14
* hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis2020-10-221-0/+9
* hw/riscv: Return the end address of the loaded firmwareAlistair Francis2020-10-221-11/+17
* load_elf: Remove unused address variables from callersBALATON Zoltan2020-09-251-4/+4
* RISC-V: Support 64 bit start addressAtish Patra2020-07-131-1/+5
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-131-4/+38
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-131-15/+38
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-131-0/+46
* riscv: Change the default behavior if no -bios option is specifiedBin Meng2020-06-031-27/+4
* riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng2020-06-031-3/+11
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-291-5/+8
* hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic2020-01-291-2/+2
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