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path: root/hw/riscv/microchip_pfsoc.c (follow)
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* hw/riscv: use qemu_configure_nic_device()David Woodhouse2024-02-021-12/+2
* riscv: spelling fixesMichael Tokarev2023-09-081-1/+1
* hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-10/+1
* hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-1/+2
* hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza2023-02-071-1/+2
* hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza2023-02-071-2/+4
* hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza2023-01-201-8/+2
* hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley2023-01-061-0/+6
* hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley2023-01-061-52/+63
* hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley2022-09-071-6/+61
* hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza2022-09-071-1/+1
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-151-1/+1
* hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1
* hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-16/+20
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-211-3/+6
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-211-1/+1
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-1/+1
* hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng2021-06-081-3/+78
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0
* hw: Do not include hw/irq.h if it is not necessaryThomas Huth2021-05-021-1/+0
* hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng2021-03-221-0/+6
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-171-0/+21
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+6
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-6/+44
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-1/+10
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-3/+6
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-5/+8
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+18
* hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng2020-11-031-0/+18
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-091-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-091-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-091-1/+5
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-091-0/+14
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-091-0/+39
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-091-0/+15
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-091-0/+23
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-091-0/+30
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-091-0/+312
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