| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-08-13 | target/arm: Fix usage of MMU indexes when EL3 is AArch32 |   Peter Maydell | 4 | -5/+12 |
| 2024-08-13 | target/arm: Clear high SVE elements in handle_vec_simd_wshli |   Richard Henderson | 1 | -0/+1 |
| 2024-08-09 | target/arm: Fix BTI versus CF_PCREL | Richard Henderson | 4 | -52/+56 |
| 2024-08-01 | target/arm: Handle denormals correctly for FMOPA (widening) | Peter Maydell | 3 | -15/+51 |
| 2024-07-29 | target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl() | Peter Maydell | 1 | -2/+16 |
| 2024-07-29 | target/arm: Fix UMOPA/UMOPS of 16-bit values | Peter Maydell | 1 | -4/+4 |
| 2024-07-29 | target/arm: Don't assert for 128-bit tile accesses when SVL is 128 | Peter Maydell | 1 | -1/+9 |
| 2024-07-23 | target/arm: Use set/clear_helper_retaddr in SVE and SME helpers | Richard Henderson | 2 | -9/+49 |
| 2024-07-23 | target/arm: Use set/clear_helper_retaddr in helper-a64.c | Richard Henderson | 1 | -2/+12 |
| 2024-07-18 | target/arm: Use FPST_F16 for SME FMOPA (widening) | Richard Henderson | 1 | -4/+8 |
| 2024-07-18 | target/arm: Use float_status copy in sme_fmopa_s |   Daniyal Khan | 1 | -1/+1 |
| 2024-07-18 | target/arm: LDAPR should honour SCTLR_ELx.nAA | Peter Maydell | 1 | -1/+1 |
| 2024-07-18 | target/arm: Fix handling of LDAPR/STLR with negative offset | Peter Maydell | 1 | -1/+1 |
| 2024-07-11 | target/arm: Convert PMULL to decodetree | Richard Henderson | 2 | -82/+15 |
| 2024-07-11 | target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree | Richard Henderson | 2 | -71/+61 |
| 2024-07-11 | target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree | Richard Henderson | 2 | -43/+48 |
| 2024-07-11 | target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree | Richard Henderson | 2 | -499/+138 |
| 2024-07-11 | target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree | Richard Henderson | 2 | -72/+87 |
| 2024-07-11 | target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree | Richard Henderson | 2 | -50/+156 |
| 2024-07-11 | target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() | Peter Maydell | 1 | -0/+1 |
| 2024-07-11 | target/arm: Rename FPCR_ QC, NZCV macros to FPSR_ | Peter Maydell | 3 | -13/+13 |
| 2024-07-11 | target/arm: Store FPSR and FPCR in separate CPU state fields | Peter Maydell | 4 | -12/+11 |
| 2024-07-11 | target/arm: Implement store_cpu_field_low32() macro | Peter Maydell | 1 | -0/+7 |
| 2024-07-05 | target/arm: Make some MTE helpers widely available |   Gustavo Romero | 2 | -38/+73 |
| 2024-07-05 | target/arm: Fix exception case in allocation_tag_mem_probe | Gustavo Romero | 1 | -0/+3 |
| 2024-07-01 | target/arm: Enable FEAT_Debugv8p8 for -cpu max | Gustavo Romero | 2 | -4/+4 |
| 2024-07-01 | target/arm: Move initialization of debug ID registers | Gustavo Romero | 1 | -3/+28 |
| 2024-07-01 | target/arm: Fix indentation | Gustavo Romero | 1 | -1/+1 |
| 2024-07-01 | target/arm: Delete dead code from disas_simd_indexed | Richard Henderson | 1 | -93/+0 |
| 2024-07-01 | target/arm: Convert FCMLA to decodetree | Richard Henderson | 2 | -170/+74 |
| 2024-07-01 | target/arm: Convert FCADD to decodetree | Richard Henderson | 2 | -23/+13 |
| 2024-07-01 | target/arm: Add data argument to do_fp3_vector | Richard Henderson | 1 | -26/+26 |
| 2024-07-01 | target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree | Richard Henderson | 2 | -28/+12 |
| 2024-07-01 | target/arm: Convert BFMLALB, BFMLALT to decodetree | Richard Henderson | 2 | -48/+31 |
| 2024-07-01 | target/arm: Convert BFDOT to decodetree | Richard Henderson | 2 | -15/+7 |
| 2024-07-01 | target/arm: Convert SUDOT, USDOT to decodetree | Richard Henderson | 2 | -27/+11 |
| 2024-07-01 | target/arm: Convert SDOT, UDOT to decodetree | Richard Henderson | 2 | -26/+35 |
| 2024-07-01 | target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree | Richard Henderson | 3 | -124/+170 |
| 2024-07-01 | target/arm: Fix SQDMULH (by element) with Q=0 | Richard Henderson | 1 | -8/+16 |
| 2024-07-01 | target/arm: Fix VCMLA Dd, Dn, Dm[idx] | Richard Henderson | 1 | -2/+2 |
| 2024-05-30 | target/arm: Implement FEAT WFxT and enable for '-cpu max' | Peter Maydell | 4 | -0/+100 |
| 2024-05-30 | target/arm: Convert FCSEL to decodetree | Richard Henderson | 2 | -63/+49 |
| 2024-05-30 | target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree | Richard Henderson | 2 | -148/+93 |
| 2024-05-30 | target/arm: Convert SQDMULH, SQRDMULH to decodetree | Richard Henderson | 3 | -196/+162 |
| 2024-05-30 | target/arm: Tidy SQDMULH, SQRDMULH (vector) | Richard Henderson | 4 | -39/+31 |
| 2024-05-30 | target/arm: Convert MLA, MLS to decodetree | Richard Henderson | 2 | -54/+31 |
| 2024-05-30 | target/arm: Convert MUL, PMUL to decodetree | Richard Henderson | 2 | -31/+25 |
| 2024-05-30 | target/arm: Convert SABA, SABD, UABA, UABD to decodetree | Richard Henderson | 2 | -16/+10 |
| 2024-05-30 | target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree | Richard Henderson | 2 | -16/+10 |
| 2024-05-30 | target/arm: Convert SRHADD, URHADD to decodetree | Richard Henderson | 2 | -8/+5 |
