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* target/mips: Use generic cpu_list()Gavin Shan2024-01-051-9/+0
* hw/mips: spelling fixesMichael Tokarev2023-08-311-1/+1
* target/mips: enable GINVx support for I6400 and I6500Marcin Nowakowski2023-07-101-2/+2
* target/mips: Add support of two XBurst CPUsSiarhei Volkau2023-07-101-0/+46
* target/mips: Implement Loongson CSR instructionsJiaxun Yang2023-07-101-0/+9
* target/mips: Set correct CP0.Config[4, 5] values for M14K(c)Marcin Nowakowski2023-03-081-2/+8
* target/mips: Implement CP0.Config7.WII bit supportMarcin Nowakowski2023-03-081-0/+3
* target/mips: Disable DSP ASE for Octeon68XXJiaxun Yang2022-11-081-2/+2
* target/mips: introduce Cavium Octeon CPU modelPavel Dovgalyuk2022-07-121-0/+28
* target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPUPhilippe Mathieu-Daudé2021-11-021-1/+0
* target/mips: Fix Loongson-3A4000 MSAIR config registerPhilippe Mathieu-Daudé2021-11-021-0/+1
* target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddrPhilippe Mathieu-Daudé2021-08-251-1/+1
* target/mips: Document Loongson-3A CPU definitionsPhilippe Mathieu-Daudé2021-08-251-2/+2
* target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2021-01-141-5/+7
* target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2021-01-141-2/+2
* target/mips: Move msa_reset() to msa_helper.cPhilippe Mathieu-Daudé2021-01-141-36/+0
* target/mips: Remove now unused ASE_MSA definitionPhilippe Mathieu-Daudé2021-01-141-4/+4
* target/mips: Simplify msa_reset()Philippe Mathieu-Daudé2021-01-141-0/+4
* target/mips: Rename translate_init.c as cpu-defs.cPhilippe Mathieu-Daudé2021-01-141-0/+1007
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